This invention relates generally to wiring structures for semiconductor devices, and more particularly to wiring structures connected to other connecting regions of the semiconductor devices through a contact hole of an interlayer insulating film employing a plug electrode to thereby electrically connect the semiconductor device connecting regions and the interconnect layer employing miniaturizing patterns of interconnect layers.
In a conventional wiring structure for a semiconductor device in the case where a via or a contact hole is formed in an interlayer insulating film, the interconnect layer is connected to a connecting region representing a lower interconnect layer or a diffusion layer formed in the surface of a semiconductor substrate or a multilayer interconnection. The acquired mechanical electrical characteristics and the resultant reliability of semiconductor device depends on the condition or state of the interconnect layer formed within the contact hole.
Reference is made to FIG. 14A illustrating a typical interconnect layer condition occurring relative to a contact hole. In FIG. 14A, a substrate 91, such as, p-type silicon, includes a deposited interlayer insulating film 93 on substrate 91 with a formed contact hole 94 through which diffusion layer 92, such as, with an n-type dopant, has been formed in the surface of substrate 91, which is followed by the formation of interconnect layer 95 comprising, for example, aluminum. The aluminum interconnect layer 95 is formed by means of deposition on the substrate 91, contact of layer 95 is made directly to diffusion layer 92. However, the deposit of the metal is not fully uniform and complete in contact hole 94, in that, for example, the metal does not deposit on the bottom corner of contact hole 94, as indicated at 94B, and forms a defective concavity or portion 95B in the form of an irregularly shaped aperture with the remaining portion of interconnect layer 95 forming an aperture verge 94A of contact hole 94. With this condition present, the contact resistance between interconnect layer 95 and diffusion layer 92 as well as the wiring resistance of interconnect layer 95 within contact hole 94 is high.
Furthermore, the disconnection of interconnect layer 95 from with contact hole 94 can easily occur. Also, in case where a multilayer interconnect is formed on the surface of substrate 91, the configuration of concavity 95B is in relief, i.e., a multitude of raised surfaces, in the upper portion of contact hole 94 so that a stepped difference or multiple stepped difference tends to occur on the upper portion of interconnect layer 95.
To correct for this situation, conventionally the internal portion of a contact hole 94 is initially filled with a plug electrode 96, as illustrated in FIG. 14B. Plug electrode 96 may be comprised of a tungsten film having good penetration quality. The use of such a single metal plug electrode of tungsten is know in the art, as set forth in the article to Carter Kaanta et al., "Submicron Wiring Technology With Tungsten and Planarization", International Device Electron Meeting, 1987, pp. 209-212. Next, interconnect layer 97, such as, aluminum, is formed on the surface of plug electrode 96. However, with the miniaturization of the pattern comprising interconnect layer 97 due to a reduce scale of circuit integration, the size of contact hole 94 becomes corresponding smaller resulting in an increase in contact resistance. Further, because only the upper surface of plug electrode 96 is connected to interconnect layer 97 at 98, the result contact area is smaller between plug electrode 96 and interconnect layer 97. The loss of contact area in this case is more accentuated when the size of contact hole becomes smaller due to a reduction of the scale of integration into the submicron range.
In addition, the process of forming interconnect layer 97 may consistently result in poor penetration relative to electrode 96 so that if a defective portion, such as, a poor contact region with electrode 96, is produced in interconnect layer 97, and there is no developed subsequent processing technique for restructure or restoring such a defective portion. As a result, a defective and nonusable integrated circuit structure is produced.
An object of this invention is to provide a method and structure for reliable mechanical and electrical connection between an interconnect layer and a connecting region such as, a diffusion layer, in a semiconductor device of an integrated circuit, even where the integration scale of the interconnect layer pattern and the integrated circuit is reduced to the sub-micron range.